Digital calculating machine



Sept. 16, 1952 W S, ELL|OTT l 2,610,790

DIGITAL CALCULATING MACHINE y.

Filed MaICh 26, 1951 (any) DELAY k CU.

NE. N92. L

ACA/vf. Aa N92 DELAY L @Gurn/Hwy) l A 00u lds/1704? la//LL/an S10/Vey ELL/Orr Patented sept. 16, 1952 UNITED" PATENT joFFica 2,610,790 DIGITAL CALCULATING MACHINE Awilliam sianenuuim, Boi-ehemwood, England Application Maich l26, 1951,l serial No.y 217,452

y nl Great-Britain March exa-195o This: invention relatesstodigital calculating and like logical machines in whichinformation is rep-` resented by sequences'of` pulses eachsequence befin'g capable of being interpreted' as a'number in the binary'scale, and isconcerned'fmore particularlywith those machines in'whicheach sequence of pulses is caused to occur in a single channel with the pulse positions'equally spaced-intime in inverse-order'to their place values in thebinary number, i. e. Withthe pulse'position-corresponding to the lowest place `value-leadingfThe -interval ottime vbetween two vsuccessivefpositions is referred to as a digiti` time,y andthe period of time occupied 'by a sequenceo'fpulses representing the largest number to be dealtA withl is referred to as a numbery time. 1

It is the object of the presentinventionto provide improved adding apparatus for use in such machines which shall perform f the "operation of combining two such sequences of kpulsesoccurrin-g during the same number time inv two different channels to form a thirdsequence of pulses repre*- senting a binary number which is the sum of the binary numbers represented lby therst two sequences. .f 'y

According to the invention, adding.l apparatus for machines of the character referred to-comprises two anti-coincidence units, two coincidence units, `a delay `unit operative to delay by one digit' time any pulse fed thereinto, and pulse channels so inter-connecting the several units 'that when' the two sequences of rpulses toA be combined are bothv fed as separate inputs both tothe iirst'anticoincidence .unit and to the rst coincidence unit, the output from the first anti-coincidence unit will constitute the one input to both the second anti-coincidence unit and the second coincidence. unit, the outputs from the 'iirst and second-'coincidence-units will constitute the input to the delay unit, the output from the delay unit will constitute the vsecond input to both the second anticoincidence unit and the second coincidence unit, and the output from the second anti-coincidence unit will yield the desired third sequence of pulses.

In this speciiication, the term "anti-coincidence unit means a two-input device or arrangement adapted to product a pulse in its output only when either of its inputs exhibits a pulse and the term coincidence unit means a twoinput device or arrangement adapted to produce a pulse in its output only when both of its inputs simultaneously exhibit pulses.

Where, as is most commonly the case, the pulses to be dealt with are electrical in nature, for

example', voltage pulses, the antilcoincidence and coincidence units preferably are or comprise elec-v tronic devices vsuch as thermionic tubes, and. the delayxun'it eithermay :be one ofthe known .delay networks or, as is preferred, may be the .'-delay network forming thesubject-matter of `the'co. pending application Serial'No,f2l7,457 ofeven date herewith. v w y The invention will be clearly understood from the following description in which l,referenceia made rto the accoinpanyingv..drawings, wherein-'- Fig. 1 is a diagram illustrating the' broad prin-` ciple upon which the invention is based, and

Fig. 2 is an electrical circuitdiagram showing one .practicalconstruction of apparatus forcarrying the invention linto eiect,.gven as an example a As can be seen from Eig. 1, the apparatuscom-fprises iirst and second anti-coincidence .funits, marked respectively -AC No. 1 and =AC No.''2'; first and second coincidence units, marked re spectively C No. 1,. and C No.2,:a1delay :unit which is marked Delay, and appropriate pulse channels connecting the several units in f the sys-- tem shown. l l o One of theY two pulse .sequences vto be added is fed'in on the input channel'markedv :1: andthe other on the input channel marked v"1,1, the pulse sequencel which -constitutesth`e output of the-apparatus appearing on the channel, marked :t4-y, which is the outputfrom'theunit AC'No. '2:F If no vpulses occur at a: and y, the outputl -Fy also *exhibits no pulse.. Should therebe a pulse at either :z: or y and no pulse at the other input-channel,r a pulse willbe fedrby AC" N o. l1 to yone input channel of each lof the units AC No. Zfand C No. 2: ytherewill'be no pulse inthe youtput of"C No. 1; vandassuming that there is no pulse tocome from the delay unit, there willbeap'ulse infth'e output :c4-y but vno pulseinthe output from C No. 2. Y* f 'f I {When a pulse occurs at eachvof the input'chan? nels riand y,'there lwill vbe no pulseiir'i'tlie' output of fAC No. 1"; a pulse willvbefed by .C,`Nc. `1j"t o. thedelay unit; and, :again assuming 'that there is no pulse to come from the delay unit, there will be no pulse in the output v-l-y and no pulse will be fed by C No. 2 to the delay unit. The pulse fed to the latter by C No. 1 will appear at the appropriate inputs to AC No. 2 and C No. 2"' at the next digit time and should there be no pulses at .r and'at y at this instant there will be delivered at output :v4-y a further pulse in this next digit time.

Without detailing the several stages, it can be stated that the occurrence of a pulse at each of the input channels a: and 'y in the next digit time to that in which a pulse was fed to the delay unit will result in a pulse in the output :c-i-y and the feeding of a further pulse to the delay unit. Similarly, the other possible occurrences will also yield the appropriate outputs.

Fig. 2 illustrates a circuit which may be utilized with great advantage in carrying the invention into practice in those cases where the pulses are voltage pulses. The input channels are again marked .r and y and the output channel is again Those portions which correspond to the blocks in the diagram of Fig. l are correspondingly marked in Fig. 2. The two anti-coincidence units follow each other at the left-hand side of the circuit diagram and are then followed by the delay unit which is succeeded by the two coincidence units. In each of the anti-coincidence units the value of the resistance R1 is made very much greater than that of either of the resistances R2 which are equal to each other. The uni-directional conducting devices indicated at D may be diodes or germanium or other suitable crystals. Both the anti-coincidence units operate in a manner which will be clear from a consideration of the circuit details without detailed explanation here. Ii? a pulse is supplied in the input a: and no pulse is supplied in the input y to the rst anticoincidence unit a pulse is derived in the output Oi oi this unit. The same result is secured if a pulse is supplied at the input y' and no pulse is supplied at the input 3:. `Should a pulse be supplied at the input :c and another at the input y simultaneously, there will be no pulse in the output O1 from this first anti-coincidence unit.l As has been said, similar considerations apply to the second anti-coincidence unit, the output of which (marked Oz) is also the output from the complete apparatus.

The manner in which the coincidence units function will be clear from a consideration of the circuit illustrated, it being understood that the valves C1 and Cz are short suppressor `base pentodes, and it will be seen that there will be no pulse in the common output O3 of these units unless a pulse is delivered by the one or other coincidence unit, and further that neither unit will deliver a pulse unless there is a pulse in each of its two inputs simultaneously. The two inputs to the ilrst coincidence unit are the .r and y inputs whereas those for the second coincidence unit are the output from the rst anti-coincidence unit and the output O4. of the delay unit. The output O4 from the latter is also supplied as one of the inputs to the second anti-coincidence unit.

The delay unit shown is that which is described in the specification of co-pending application Serial No. 217,457 of even date herewith, and is arranged to cause a delay of one digit time in the passage of any pulse which may be delivered to the delay unit from the output Oa of the coincidence units. Since the delay unit vfunctions due to the inclusion of the inductances Li and L2 in its input and output sides, respectively, the shape of propriate points in the circuit, as will be appreci- Y ated from a consideration oi the latter.

What I claim is: 1. An adding unit for a binary digital calculating machine comprising first and second anti-coincidence units, first and second coincidence umts,

and a delay unit operative to delay by one digit time any-puise fed thereto, a first pulse input channel each of the 'rst anti-coincidence unit and the first coincidence unit for receiving the ilrst of the two separate pulse sequences to be added, a second pulse input channel to each oi the said ilrst anti-coincidence and coincidence units for simultaneously receiving the other of the two pulse sequences. and pulse transmitting channels interconnecting the said units, as follows: a channel connecting the output from the first anti-coincidence unit to the one inputs of both the second anti-coincidence unit and the second coincidence unit; a channel connecting the output of each of the first and second coincidence units t0 the delay unit; a channel connecting the output from the delay unit to each of the other inputs ot the second anti-coincidence and coincidence units; and a resultant output channel from the second anti-coincidence unit.

2. In an adding unit as claimed in claim l, an anti-coincidence unit comprising a pair of similarv multi-electrode thermionic tubes each having a control grid constituting a respective input to the unit, a pair of equal resistances constituting respectively the anode loads of the tubes, and a pair of unidirectional conducting devices similarly connected between the respective anodes and a common output channel. v

. 3. An anti-coincidence unit as claimed in claim 2, wherein the cathode circuits of the two tubesV are commoned and the said common circuit includes a resistance whose value is large compared with that of the anode load resistances.

4. In an adding unit as claimed in claim 1, a

coincidence unit comprising a thermionic tube having at least two grids. each of said constituting a pulse input to the unit.

5. In an adding unit as claimed in claim 1, a pair of coincidence units each comprising a thermlonic tube having at least two grids constituting the inputs to the unit, a common anode load resistance for both tubes, and a common output channel from the anode of both tubes.

WILLIAM SIDNEY ELLIO'I'I.

No references cited. 

